Google, TU Delft Develop New FA Hardware Solution for Complex ICs
Researchers from Google and Delft University of Technology have developed a new Failure Analysis (FA) hardware solution that enables System-Level FA on mobile System-on-a-Chip (SoC) PoP devices. The primary challenge in performing FA on the bottom die is providing direct line-of-sight access while preserving the top DRAM functionality through extremely small interconnects called Through Interposer Vias (TIVs).
The new hardware solution overcomes this challenge by utilizing a small interposer pin pitch of approximately 210 um and advanced DRAM card design that incorporates stringent design rules. This enables up to 6.3 Gbps using a DDR training test and allows for standard Android stress applications.
The researchers published their findings in the technical paper 'Innovative FA Hardware Solution to Enable System-Level Debug of 3D ICs' in the Microelectronics Reliability journal in 2026. The research aims to improve the efficiency of failure analysis on complex integrated circuits and enable more accurate debugging at the system level.