IBM Unveils Mainframe Processors with Dual Arm and Z Architecture Support

IBM has introduced its latest mainframe processor series, which supports two instruction sets simultaneously: its native Z architecture and Arm. The new processor series is designed for high-performance computing in mission-critical applications.

The new dual-ISA processor will be part of IBM's z18 generation, with a 2nm process node and 11 cores per chip, each with 5.7 GHz+ clock speeds. It features simultaneous multithreading (SMT) technology, processing two threads per core.

Each core supports both the Z architecture and Arm instruction sets, specifically ArmV9.3, including SVE and SVE2, with a total of 2792 Arm instructions supported. The processor has a large private L2 cache of 36 MB per core and a virtual L4 cache of 3.5 GB.

IBM's new mainframe processors will be used in the z18 generation, which is designed for high-performance computing in mission-critical applications with 99.999999% availability.