ParityQC Unveils Parity Twine Optimizer in IBM Qiskit Functions Catalog
ParityQC has launched its Parity Twine Optimizer through IBM's Qiskit Functions Catalog. The software module operates on the ParityQC Architecture, a variant of the Lechner-Hauke-Zoller (LHZ) architecture, and eliminates classical SWAP gate overhead by mapping optimization problem graphs natively onto physical Quantum Processing Unit (QPU) coupling maps.
The compiler technology was validated in recent Quantum Fourier Transform (QFT) compilation benchmarks. It is engineered to optimize quadratic unconstrained binary optimization (QUBO) and combinatorial optimization algorithms across both NISQ and fault-tolerant hardware topologies.
The Parity Twine Optimizer reduces two-qubit gate count and circuit depth by bypassing routing SWAP networks, allowing larger and more highly connected problem graphs to execute on fixed hardware layouts. It natively supports heavy-hex architectures (such as the IBM Heron QPU) and square-lattice topologies (such as the IBM Nighthawk QPU).